A display device (e.g., a liquid crystal panel) includes an array substrate, and generally, the array substrate includes a plurality of pixel units. FIG. 1 is a schematic diagram illustrating a structure of a pixel unit of a conventional array substrate. As shown in FIG. 1, the pixel unit of the array substrate includes at least a thin film transistor 100′ and a pixel electrode 200, the thin film transistor 100′ includes at least a source 110, a drain 120 and a gate 130, the pixel electrode 200 is electrically connected to the drain 120 of the thin film transistor 100′ through a via hole 300′. In the array substrate, in order to reduce parasitic capacitance and improve flatness of an upper surface of the thin film transistor 100′, an organic insulation layer 140 is generally provided above the source 110 and the drain 120 of the thin film transistor 100′ as a planarization layer. The greater thickness of the organic insulation layer 140 is, the smaller the parasitic capacitance becomes. However, thickness increment of the organic insulation layer may cause increase in axial height of the via hole 300′. The greater the axial height of the via hole 300′ is, the more likely the pixel electrode 200 fractures at a joint with the via hole 300′.
Consequently, how to avoid the fracture of the pixel electrode at the joint with the via hole while reducing the parasitic capacitance becomes the technical problem to be solved in the art.